Design verification engineer - technical lead, annapurna labs
TorontoAmazon Development Centre Canada ULC
...a better-rounded professional and enable them to take on more complex tasks in the future. - 8+ years of design verification experience using constrained-random simulation techniques (such as UVM) - 8+ years of experience in testbench development including stimulus, checkers, assertions and coverage - Experience with C/C++ and [...]
Category Engineering & Architecture